Performance evaluation of multipliers in reconfigurable hardware

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JNSF-36(3)-235.pdf (95.87 KB)

Date

Authors

Wijesinghe, W.A.S.^dDepartment of Electronics^fFaculty of Applied Sciences^iWayamba University of Sri Lanka^pMankandura

Jayananda, M.K.^dDepartment of Physics^fFaculty of Science^iUniversity of Colombo^pColombo 03

Sonnadara, D.U.J.^dDepartment of Physics^fFaculty of Science^iUniversity of Colombo^pColombo 03

Publisher

National Science Foundation:Colombo

Keywords

Information Communication Technology, Computer hardware, Multiplier hardware architecture, Field programmable gate array (FPGAs), Reconfigurable computing, Resource utilization, Hardware description Language (VHDL), Computer Science

Citation

Journal of the National Science Foundation of Sri Lanka, 36(3):p.235-237

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http://vidya.nsf.gov.lk:8080/pdfs/JNSF-36(3)/JNSF-36(3)-235.pdf
https://viduketha.nsf.gov.lk/handle/123456789/358

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Journal of the National Science Foundation of Sri Lanka (JNSF)