Performance evaluation of multipliers in reconfigurable hardware

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dc.contributor.authorWijesinghe, W.A.S.^dDepartment of Electronics^fFaculty of Applied Sciences^iWayamba University of Sri Lanka^pMankandura
dc.contributor.authorJayananda, M.K.^dDepartment of Physics^fFaculty of Science^iUniversity of Colombo^pColombo 03
dc.contributor.authorSonnadara, D.U.J.^dDepartment of Physics^fFaculty of Science^iUniversity of Colombo^pColombo 03
dc.date.accessioned2026-07-09T15:34:46Z
dc.date.issued2008
dc.identifier.citationJournal of the National Science Foundation of Sri Lanka, 36(3):p.235-237
dc.identifier.urihttp://vidya.nsf.gov.lk:8080/pdfs/JNSF-36(3)/JNSF-36(3)-235.pdf
dc.identifier.urihttps://viduketha.nsf.gov.lk/handle/123456789/358
dc.language.isoEnglish
dc.publisherNational Science Foundation:Colombo
dc.subjectInformation Communication Technology
dc.subjectComputer hardware
dc.subjectMultiplier hardware architecture
dc.subjectField programmable gate array (FPGAs)
dc.subjectReconfigurable computing
dc.subjectResource utilization
dc.subjectHardware description Language (VHDL)
dc.subjectComputer Science
dc.titlePerformance evaluation of multipliers in reconfigurable hardware
dc.typeArticle

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