A simple reconfigurable microprocessor in a 36 macrocell CPLD

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JNSF39_3_261.pdf (94.12 KB)

Date

Authors

Wijesinghe, W.A.S.^iDepartment of Electronics, Faculty of Applied Sciences, Wayamba University of Sri Lanka^pMakandura

Jayananda, M.K.^iCentre for Instrument Development, Department of Physics, Faculty of Science, University of Colombo^pColombo

Sonnadara, D.U.J.^iCentre for Instrument Development, Department of Physics, Faculty of Science, University of Colombo^pColombo

Publisher

NSF:Colombo

Keywords

Information Communication Technology, Data acquisition, Complex programmable logic device (CPLD), Field programmable gate arrays (EPGA), Microcontrollers, Reconfigurable computing, Hardware description language, VHDL

Citation

Journal of the National Science Foundation of Sri Lanka, 39(3):p.261-266

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http://vidya.nsf.gov.lk:8080/pdfs/JNSF-39(3)/JNSF39_3_261.pdf
https://viduketha.nsf.gov.lk/handle/123456789/715

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Journal of the National Science Foundation of Sri Lanka (JNSF)