An efficient and improved algorithm for generating an equivalent planar architecture of the data vortex switch

Abstract

The data vortex (DV) switch was originally designed as an all optical interconnection network for high performance computing (HPC) applications. It was highly scalable with low latency and high throughput, compared to traditional switches used for optical packet switching (OPS) and HPC applications. The equivalent planar (chained MIN) model of the DV, proposed in previous literature, is a planar diagrammatic conversion of a 3-D model of the DV network. In this paper, we will focus on exploring a new, efficient and improved generalized algorithm that enables the arrangement of routing pathways to be implemented as an equivalent planar architecture (EPA, chained MIN) of a DV to find all possible routes between each source and target node pair. The original 3-D architecture of any size can be converted to a planar structure more simply by using the new generalized equivalent planar architecture (EPA) algorithm. To verify the proposed EPA algorithm, it was tested with different input traffic loads and network sizes while keeping the active angle ‘A’ constant. Network performance parameters, including injection rate (throughput) and latency (mean hops), obtained from simulation results are also provided to confirm the validity of the proposed EPA algorithm. This new algorithm is versatile, simple and can be applied to networks of various sizes.